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| hc908jb16ad/d rev. 1, 8/2002 addendum to mc68hc908jb16 te c h n i c a l d a t a addendum this addendum provides update and additional information to the mc68hc908jb16 technical data , rev. 1 (motorola document num ber mc68hc908jb16/d), pertaining to the following: ? mc68hc908jb16 ? update to v reg lvi trip point ? 20-pin soic package MC68HC908JB12 mc68hc08jb16 mc68hc908jb16 this section updates data sheet inform ation and introduces the 20-pin soic package for the mc68hc908jb16. v reg lvi trip point page 318, entry for minimum v reg lvi trip point voltage has been updated. from: to: characteristic symbol min typ max unit v reg lvi trip point voltage v lv r 2.0 2.2 2.6 v v reg lvi trip point voltage v lv r 1.9 2.2 2.6 v f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
hc908jb16ad/d addendum to mc68hc908jb16 technical data 20-pin soic order number: mc68hc908jb16jdw figure 1. 20-pin soic pin assignment figure 2. 20-pin soic mechanical dimensions (case no. 751d) 1 2 3 4 5 6 7 20 19 18 17 16 15 14 13 12 11 8 9 10 osc1 pta0/kba0 rst pta1/kba1 pta2/kba2 pta3/kba3 pta4/kba4 pta5/kba5 pta6/kba6 pta7/kba7 irq osc2 vreg vdd ptd0/1 pte1/t1ch01 pte3/d+ pte4/d? ptc0/txd vss internal pads are unconnected. ptd0/1 pin: ptd0 and ptd1 internal pads are bonded together to ptd0/1 pin, and has 50ma sink capability when configured as an output. pin direction must be confi gured such that ddrd0 = ddrd1. pins not available on 20-pin package: ptc1/rxd pte0/tclk ptd2 pte2/t2ch01 ptd3 cgmxfc1 cgmxfc2 ptd4 cgmout1 cgmout2 ptd5 vrega0 vrega1 vssa0 vssa1 vdda notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ?a? ?b? 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c ?t? seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d MC68HC908JB12 addendum to mc68hc908jb16 technical data MC68HC908JB12 this section introduces the MC68HC908JB12, a derivative of the mc68hc908jb16. the entire mc68hc908jb16 data book, including the updates in this addendum, applies to th is device, with exceptions outlined below. mcu block diagram figure 3 shows the structure of the MC68HC908JB12. memory map figure 4 shows the memory map of the MC68HC908JB12. dual clock generator module the dual 27-mhz clock generator modul e on the mc68hc908jb16 is not designed in the MC68HC908JB12, hence, register locations from $0051 to $0059 are unimplemented. information in the data book relating to the cgm do not apply to the MC68HC908JB12. table 1. summary of MC68HC908JB12 and mc68hc908jb16 differences MC68HC908JB12 mc68hc908jb16 flash memory 12,288 bytes ($ca00?$f9ff) 16,384 bytes ($ba00?$f9ff) dual clock generator module not implemented. $0051?$0059 unimplemented. available in 32-pin lqfp only. available packages (1) ? 28-pin soic 20-pin soic 32-pin lqfp 28-pin soic 20-pin soic notes : 1. the pin assignments are identical for both devices; see data sheet. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d addendum to mc68hc908jb16 technical data figure 3. MC68HC908JB12 block diagram system integration module 2-channel timer interface module 1 low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 128 bytes user flash memory ? 12,288 bytes user ram ? 384 bytes monitor rom ? 1,472 bytes user flash vectors ? 48 bytes power and internal pta ddra ddre pte internal bus usb module usb endpoint 0, 1, 2 ls usb transceiver break module oscillator ptc ddrc keyboard interrupt module power-on reset module (1) osc1 (1) osc2 (2) rst (3) irq v dd v ss v reg (3.3v) 2-channel timer interface module 2 serial communications interface module irq module voltage regulators pte0/tclk (3), (6) pte1/t1ch01 (3) pte2/t2ch01 (3), (6) pte3/d+ (3), (4) pte4/d? (3), (4) ptc1/rxd (3), (6) ptc0/txd (3) pta7/kba7 pta0/kba0 (1) pins have 3v logic. (2) pins have integrated pullup device. (3) pins have software co nfigurable pullup device. (4) pins are open-drain when configured as output. : (3) (6) pins available on 28-pin package only. ddrd ptd ptd0 (4), (7) ptd1 (4), (7) ptd2 (4), (6) ptd3 (4), (6) ptd4 (4), (6) ptd5 (4), (6) (7) on 20-pin package, ptd0 and ptd1 are bonded as a single ptd 0/1 pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d MC68HC908JB12 addendum to mc68hc908jb16 technical data $0000 $007f i/o registers 128 bytes $0080 $01ff ram 384 bytes $0200 $c9ff unimplemented 51,200 bytes $ca00 $f9ff flash memory 12,288 bytes $fa00 $fdff monitor rom 1 1,024 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 reserved $fe08 flash control register (flcr) $fe09 flash block protect register (flbpr) $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f reserved $fe10 $ffcf monitor rom 2 448 bytes $ffd0 $ffff flash vectors 48 bytes figure 4. MC68HC908JB12 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d addendum to mc68hc908jb16 technical data pullup on pte3/d+ and pte4/d? pins on the MC68HC908JB12, control over the pullup devices on pte3/d+ and pte4/d? pins are shown in table 2 . electrical specifications electrical specifications for the mc68hc908jb16 apply to the MC68HC908JB12, except for the usb reset timing: order numbers these are mc order numbers for MC68HC908JB12. table 2. pullup control on pte3/d+ and pte4/d? pins pullen ($001a) usben ($0038) ptexp ($001d) pte4ie ($001c) pte3/d+ pin pte4/d? pin 0000 ? ? 00105k ? pullup to v dd 5k ? pullup to v dd (1) 0001 ? 5k ? pullup to v dd (1) 00115k ? pullup to v dd 5k ? pullup to v dd (1) 01xx ? ? 11xx ? 1.5k ? pullup to v reg 10x0 ? 1.5k ? pullup to v reg 1 0 x 1 do not set this configuration. notes : notes : 1. external interrupt function is also enabled on pte4/d? pin. bus state signaling levels transmit receive reset na d+ and d? < v il (max) for 8 s (mc68hc908jb16) d+ and d? < v il (max) for 125 s (MC68HC908JB12) table 3. MC68HC908JB12 order numbers mc order number package operating temperature range MC68HC908JB12jdw 20-pin soic 0 c to +70 c MC68HC908JB12dw 28-pin soic 0 c to +70 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d mc68hc08jb16 addendum to mc68hc908jb16 technical data mc68hc08jb16 this section introduces the mc68hc08jb16, the rom part equivalent to the mc68hc908jb16. the entire mc68hc908jb16 data book applies to this rom device, with exceptions outlined below. mcu block diagram figure 5 shows the block diagram of the mc68hc08jb16. memory map figure 6 shows the memory map of the mc68hc08jb16. reserved registers the two registers at $fe08 and $ff09 are reserved locations on the mc68hc08jb16. on the mc68hc908jb16, these two locations are the flash control register and the flash block protect register respectively. monitor rom the monitor program (monitor rom, $fe10?$ffcf) on the mc68hc08jb16 is for device testing only. table 4. summary of mc68hc08jb16 and mc68hc908jb16 differences mc68hc08jb16 mc68hc908jb16 memory ($ba00?$f9ff) 16,384 bytes rom 16,384 bytes flash user vectors ($ffd0?$ffff) 48 bytes rom 48 bytes flash registers at $fe08 and $fe09 not used; locations are reserved flash related registers. $fe08 ? flcr $fe09 ? flbpr monitor rom 1 ($fa00?$fdff) unimplemented used for testing and flash programming/erasing. monitor rom 2 ($fe10?$ffcf) used for testing purposes only. dual clock generator module currently not available. availa ble in 32-pin lqfp only. available packages (1) 32-pin lqfp currently not available. 28-pin soic 20-pin soic 32-pin lqfp 28-pin soic 20-pin soic notes : 1. the pin assignments are identical for both devices; see data sheet. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d addendum to mc68hc908jb16 technical data figure 5. mc68hc08jb16 block diagram system integration module 2-channel timer interface module 1 low voltage inhibit module computer operating properly module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 128 bytes user rom ? 16,384 bytes user ram ? 384 bytes monitor rom ? 448 bytes user rom vectors ? 48 bytes power and internal pta ddra ddre pte internal bus usb module usb endpoint 0, 1, 2 ls usb transceiver break module oscillator ptc ddrc keyboard interrupt module power-on reset module (1) osc1 (1) osc2 (2) rst (3) irq v dd v ss v reg (3.3v) 2-channel timer interface module 2 serial communications interface module irq module dual clock generator module (5) cgmxfc1 (1), (5) cgmout1 (5) cgmxfc2 (1), (5) cgmout2 voltage regulators pte0/tclk (3) pte1/t1ch01 (3) pte2/t2ch01 (3) pte3/d+ (3), (4) pte4/d? (3), (4) ptc1/rxd (3) ptc0/txd (3) pta7/kba7 pta0/kba0 (1) pins have 3v logic. (2) pins have integrated pullup device. (3) pins have software co nfigurable pull-up device. (4) pins are open-drain when configured as output. (5) pins available on 32-pin package only. : (3) (5) v dda (5) v ssa0 (5) v ssa1 (6) pins available on 28-pin package only. (5) v rega1 (3.3v) (5) v rega0 (3.3v) ddrd ptd ptd0 (4) ptd1 (4), (6) ptd2 (4), (6) ptd3 (4), (6) ptd4 (4), (6) ptd5 (4), (6) shaded blocks indicate diffe rences to mc68hc908jb16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d mc68hc08jb16 addendum to mc68hc908jb16 technical data $0000 $007f i/o registers 128 bytes $0080 $01ff ram 384 bytes $0200 $b9ff unimplemented 47,104 bytes $ba00 $f9ff rom 16,384 bytes $fa00 $fdff unimplemented 1,024 bytes $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 reserved $fe08 reserved $fe09 reserved $fe0a reserved $fe0b reserved $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f reserved $fe10 $ffcf monitor rom 448 bytes $ffd0 $ffff rom vectors 48 bytes figure 6. mc68hc08jb16 memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d addendum to mc68hc908jb16 technical data electrical specifications electrical specifications for the mc68hc908jb16 apply to the mc68hc08jb16, except for the following: flash memory characteristics the flash memory electrical characteristics do not apply to the mc68hc08jb16 rom device. rom mc order numbers these part numbers are generic number s only. to place an order, rom code must be submitted to the rom processing center (rpc). table 5. rom mc order numbers mc order number package operating temperature range mc68hc08jb16jdw 20-pin soic 0 c to +70 c mc68hc08jb16dw 28-pin soic 0 c to +70 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d notes addendum to mc68hc908jb16 technical data notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . hc908jb16ad/d rev. 1 8/2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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